1. Field of Invention
The present invention relates to Read-Only Memory (ROM) cell structures and, more particularly, to high density, high performance ROM cell structures.
2. Description of the Prior Art
Several ROM cell structures that read out cell data are well known in the art. One approach is referred to as the flat-cell ROM design. As with most integrated circuit design, speed, size, power and ease of fabrication, rank among the most important design considerations in the design. Improving speed while lowering power consumption and minimizing size are goals of most integrated circuit design. Furthermore, it is desirable to simplify design to allow for easier fabrication techniques which in turn will decrease the cost of manufacture.
One method of optimizing ROM cell structure performance in terms of speed, size, power consumption and ease of design, is to limit the number of transistors used in a particular circuit. Additionally, optimal use of semiconductor surface area will provide semiconductor devices smaller in size and easier to fabricate. The flat cell design gives a very small area per storage unit cell (ROM cell) compared to other known design approaches.
In a flat-cell field-effect transistor (FET), unlike the traditional Local Oxidation Silicon (LOCOS) approach to FET design, the width of the polysilicon word line defines the channel width of the FET, rather than the channel length. This allows a designer to pack the polysilicon lines in the ROM cores purely from the point of view process limitations, rather than the FET device's physical limitations. Also, because there is no thermally grown field oxide in the core ROM cell region, there is no channel width reduction due to birdsbeak in the field oxide. This allows a very dense core array to be achieved.
However, the size of the ROM cell does not alone determine the size of the ROM array. The circuitry required to access the ROM cell and other peripheral circuits also contributes to the overall size of the array. Therefore, limiting the number of transistors required in the circuitry for accessing the ROM can optimize speed, size and power consumption.
Also, in a flat-cell ROM, the local bit lines are fabricated with buried diffusion, and have relatively high resistance and capacitance associated with them. Thus, it is difficult to drive the buried diffusion lines quickly. In order to overcome the speed problem with the buried diffusion bit lines, metal lines running parallel with the buried diffusion lines, and making contacts with them every so often, are used in the prior art. However, the core ROM cell pitch becomes limited by the metal and contact pitches, rather than the basic transistor pitches, and loses packing advantages.
A prior art flat-cell ROM design can be found in U.S. Pat. No. 5,117,389 of Yiu, entitled "Flat-Cell Read-Only-Memory Integrated Circuit." In the Yiu reference the flat-cell ROM array uses block select transistors to allow for the layout of straight metal lines. The circuit design of Yiu is shown in FIG. 1 which corresponds to FIG. 4 of Yiu. The circuitry required to access the ROM cell of Yiu utilizes a minimum of 4 transistors. FIG. 1 shows the integrated circuit of Yiu requires a block select transistor (BWL.sub.N), word select transistor (SWL.sub.N), bank left select transistor (SBL.sub.N), and a bank right select transistor (SBR.sub.N) to access a ROM cell. One disadvantage of the ROM design of Yiu is in the number of transistors required to access the ROM cell, which affects the overall size of the array. Other peripheral circuits also contribute to the overall array size.
FIG. 2 also shows a ROM cell array found in Japanese patent application no. 6375300. The integrated circuit of FIG. 2 requires the use of a minimum of 3 transistors to access information found in the ROM sub-array. However, the integrated circuit of FIG. 2 suffers from several disadvantages. For example, the resistance of the read path of the circuit of FIG. 2 from the sense amplifier through the cell selector and cell transistors to ground is not fixed. If, for example, it is desired to read an odd cell on word line WL0, the signal must travel the additional length that extends to transistor SO.sub.j. In contrast, if it is desired to read an odd cell on word line WL15, the signal travels a much shorter length to transistor SO.sub.i. Thus the signal path resistance when reading the cell on WL15 is much less than the resistance when reading the cell on WL0. Since the signal path resistance affects the data access time (RC delay), the data access time in this structure is not fixed. Further, the layout of the cell loses packing advantages. As a result, the buried N+resistance could become too large. Additionally, the layout does not allow for straight metal bit lines. The zig-zag metal bit lines (6, 7) of FIG. 2 cause metal bit lines of a smaller pitch in the regions where the lines jog. This complicates the manufacturing process.
Therefore, it is desirable to design a high performance ROM, while maintaining high packing densities offered by the flat-cell design technique, which can be manufactured with high yield. It is also desirable to utilize straight metal bit lines to simplify manufacture and increase circuit efficiency. It is also desirable to minimize the number of transistors in an array in order to optimize speed, size, power consumption and ease of fabrication parameters.